1. Field of the Invention
The invention generally relates to computer systems and, in particular, to computer systems employing a memory controller and a graphics controller.
2. Related Applications
The present application is related to U.S. Pat. No. 5,818,464 entitled, "Method and Apparatus for Arbitrating Access to a Shared Computer System Memory by a Graphics Controller and a Memory Controller," issued Oct. 6, 1998 and incorporated herein by reference.
3. Description of Related Art
Typical computer systems employing a microprocessor utilize a memory controller and a graphics controller. The memory controller controls access by the microprocessor and other peripheral integrated circuits (IC) to system memory. The graphics controller controls display of data provided by the microprocessor onto a display screen using a frame buffer. Both the system memory and the frame buffer are typically implemented using arrays of dynamic random access memory (DRAM) chips. In such systems, the memory controller and microprocessor cannot directly access the frame buffer and the graphics controller cannot directly access the system memory.
Certain disadvantages arise from providing a frame buffer which is separate from system memory. For example, if all or a portion of a frame buffer is not in use, it would be desirable to allow unused portions of the frame buffer memory to be employed as system memory. This cannot easily be achieved with a separate frame buffer controlled by a graphics controller.
One proposed solution to the foregoing problem is to provide a single array of DRAM memory chips accessible through a single interface bus by both the memory controller and the graphics controller. The memory space provided by the single array is partitioned between system memory and frame buffer memory. In such a system, the memory controller may access the frame buffer portion of memory for use as system memory. Also, certain graphics operations may be expedited by allowing both the graphics controller and the memory controller to write graphics data into the frame buffer. For example, a set of individual graphics operations may be pipelined with some operations performed through the graphics controller and others through the memory controller in rapid succession. Another advantage of such a system is that the size of the portion of memory devoted to the frame buffer may be easily modified based upon the needs of the system.
Hence, in such a system, both the memory controller and the graphics controller can access the same array of physical memory through a single interface bus. An arbitration mechanism must be employed to prevent conflicts between the memory controller and the graphics controller. An appropriate arbitration mechanism is set forth in the above-referenced co-pending patent application. A management system should also be employed to control access to the shared memory by software running on the microprocessor including operating system software and applications software. For example, operating system software must be prevented from corrupting the frame buffer portion of the shared memory while that portion of the shared memory is being used as a frame buffer by the graphics controller. Such corruption could occur if, for example, operating system software swaps data into or out of the frame buffer portion of the shared memory. On the other hand, to gain the benefit of having additional system memory when a frame buffer is not required, application software should be able to access all portions of the shared memory.
The foregoing software access issues are particularly problematic in systems employing paging, such as systems employing a microprocessor configured in accordance with Intel Architecture. Page tables must be defined and accessed in such a manner that corruption of data contained within the frame buffer does not occur. Software access issues are also particularly problematic in systems employing caches wherein a portion of data contained within the frame buffer may be cached, for example, within an L1 cache within the microprocessor or within an L2 cache connected to the memory controller, or within both. In such systems, cache coherency must be maintained. Accordingly, it would be desirable to provide a method and apparatus for controlling software access to a shared computer system memory, particularly for a system employing caching and paging, and aspects of the present invention are drawn to such a method and apparatus.
As noted above, one of the advantages of providing a shared computer system memory is that graphics operations within the frame buffer portion of the memory may be performed directly by the microprocessor through the memory controller, rather than through the graphics controller. However, circumstances may arise where the memory controller may be busy performing needed memory operations, such as DRAM refresh operations, and graphics commands issued by the microprocessor therefore cannot be performed immediately through the memory controller. In systems where memory operations can be buffered between the microprocessor and the memory controller, perhaps in a FIFO buffer, circumstances may arise where the buffer becomes full, possibly resulting in a stall of the microprocessor. Accordingly, it would be desirable to provide an improved method and apparatus for expediting the execution of graphics operations generated by the microprocessor within a system employing a shared memory. Further aspects of the invention are drawn to such an improved method and apparatus.
In systems employing microprocessors capable of performing sophisticated graphics operations, such as those normally performed by graphics controller, it would be desirable to implement a shared computer memory system which allows the microprocessor to perform almost all computer graphics operations. Others aspects of the invention are drawn to such an implementation.
Another problem with implementing a shared computer system memory accessible through only a single interface bus is that access to the memory by the memory controller must be frequently blocked to allow the graphics controller to perform frame buffer refresh operations. In a typical proposed implementation, such frame buffer refresh operations must be performed fairly frequently. Accordingly, considerable bus bandwidth must be devoted to handling frame buffer refresh operations. Accordingly, it would be desirable to provide an improved method and apparatus for partitioning the system memory and the frame buffer memory within the shared memory to minimize the impact on total bus bandwidth by frame buffer refresh operations. Other aspects of the invention are drawn to such an improved partitioning.